1. Field of the Invention
This invention relates generally to clock supply devices and more particularly to a method and apparatus for reducing the skew of a clock signal that is distributed to memory elements in a synchronous memory device.
2. Description of the Related Art
In a conventional clock supply device for a memory chip, a TTL level clock signal is provided from the system, received inside a memory chip, converted to a CMOS level after passing through a buffer, and then used for the clock signal of the memory. Thus, the conventional clock supply device has a prescribed signal delay characteristic between the point where the source clock signal is received from the system and the point where it is distributed and switched to internal elements of the memory.
In a synchronous memory device, which operates in synchronization with the clock signal that is input from the system, the clock supply device employs a built-in delay locked loop (DLL) or phase locked loop (PLL) circuit to accurately supply the system clock signal to the internal elements of the memory.
FIG. 1 is a block diagram of a prior art clock supply device which utilizes a DLL circuit for distributing a system clock signal to the internal elements of a memory device. Referring to FIG. 1, the conventional clock supply device includes a clock generating section 10, which is located at a first position inside the memory, for generating a clock signal for the system. A clock distributing section 20, which is located at a second position inside the memory, distributes the clock signal. A DLL 14 produces a clock signal which is locked with the system clock signal that is generated by the clock generating section 10. A clock transmitting section 18 transmits the clock signal from the DLL 14 to the clock distributing section 20 with a prescribed signal delay characteristic. A clock transmission compensating section 16 compensates for the signal delay characteristic of the clock signal transmitted through the clock transmitting section 18 (typically a transmission line).
In a conventional clock supply device as constructed above, the source clock signal for the system is generated by the clock generating section 10 which is placed at the first position inside the memory.
The source clock signal is applied to the DLL 14, and the delayed clock signal is detected by a phase discriminator 11. The clock delay detected by the phase discriminator 11 is controlled by a charging pump 12. A delay cell 13 varies the clock delay controlled by the charging pump 12 so that the clock delay is locked with the source clock signal.
Although the clock signal provided by the DLL 14 is locked with the source signal, a prescribed signal delay occurs while the clock signal is transmitted through a bus line to the clock distributing section 20 which is located at the second position inside the memory. Therefore, to compensate for the prescribed clock delay which occurs when the clock signal is propagated through the clock transmitting section 18, the clock signal which is output from the DLL 14 is fed back to the DLL through the clock transmission compensating section 16 which compensates for the prescribed clock delay. The clock signal from the DLL 14 is locked with the source clock signal, and is then output to the clock distributing section 20.
FIG. 2 is a block diagram of a second prior art clock supply device which utilizes a PLL circuit for distributing a clock signal to the internal elements of a memory system. Referring to FIG. 2, the conventional clock supply device includes a clock generating section 22, which is located at a first position inside the memory, for generating a clock signal for the system. A clock distributing section 32, which is located at a second position inside the memory, distributes the clock signal. A PLL 26 produces a clock signal which is locked with the phase of the system clock signal that is generated by the clock generating section 22. A clock transmitting section 30 (typically a transmission line) transmits the clock signal from the PLL 26 to the clock distributing section 32 with a prescribed signal delay characteristic. A clock transmission compensating section 28 compensates for the signal delay characteristic of the clock signal transmitted through the clock transmitting section 30.
The operation of the clock supply device of FIG. 2 is similar to that of the device of FIG. 1 even though the DLL is replaced by a PLL. Thus a more detailed explanation of the operation of the device of FIG. 2 will be omitted.
In the prior art clock supply devices of FIGS. 1 and 2 as described above, the operation characteristics of the clock transmission compensating sections 16 and 28 are sensitive to variations in the external environment, process, temperature, etc. The operating characteristics of the clock transmitting sections 18 and 30 are also sensitive to such changes, and thus it is difficult for the circuits to lock the clock signals from the clock distributing sections 20 and 32 with the source clock signals from the clock generating sections 10 and 22.
Thus, since the skew of the clock signal is likely to change along the bus lines between the points at which the source clock signal is received from the system and the point at which it is applied and switched to the internal elements of the memory, the phase of the source clock signal is not accurately synchronized with the internal elements of the memory. This results in the generation of undesirable jitter.
Accordingly, a need remains for a technique for overcoming the problems of the prior art.